1. Field of the Invention
The present invention relates to an interrupt control method for controlling an interrupt from a peripheral device, such as an input/out device, to a processor.
2. Description of the Related Art
In a computer system formed of a processor and a plurality of peripheral devices, such as an input/output device, various interrupt control methods are known for executing a predetermined instruction after an interrupt is sent from a peripheral device to the processor. In general, the interrupt operation is started in accordance with the transmission of an interrupt request and an interrupt vector from the peripheral device to the processor, and executed based on an interrupt acknowledge by the processor.
Recently, since the performance of computers has generally increased, it is very important to realize effective interrupt operation in order to increase the throughput of a system.
In a conventional art, the Japanese Unexamined Patent Publication (KOKAI) No. 63-271537 and No. 4-373056, have disclosed as two representative methods as explained below.
The former (JPP-63-271537) discloses an interrupt controller which can change the interrupt vector generated by a numerical operation processor. That is, in a computer system including a microprocessor and a numerical operation processor, interrupt vectors were previously fixed and only fixed interrupt vectors were sent from the numeral operation processor to the microprocessor. However, according to this citation, an interrupt controller is newly provided between the microprocessor and the numerical operation processor so that it is possible to change the interrupt vector from the numerical operation processor.
In this case, the citation discloses only a change in the interrupt vector from the numerical operation processor, and it does not disclose a change in the interrupt vector which is required in accordance with the change of the system structure.
The latter (JPP-4-373056) also discloses an interrupt controller which can change the priority order of interrupt requests from a peripheral device. That is, in a computer system including an interrupt controller and a plurality of peripheral devices, the priority order of the interrupt requests from peripheral devices was fixedly determined in a conventional system. However, in this citation, when the interrupt controller simultaneously receives a plurality of interrupt requests from the peripheral devices, the interrupt controller can change the priority order of the interrupt requests in accordance with the frequency of the individual interrupt requests.
In this case, the citation discloses only a change in the priority order of the interrupt requests from the peripheral devices, and does not disclose a change of interrupt request which is required in accordance with the change of the terms of use of the system or the condition of the system in use.